2nm hasn't been used yet. 0.7nm has been waiting.

IBM introduced the world's first sub-1nm (Sub-1nm) chip technology at VLSI 2026, unveiling a new transistor architecture called NanoStack, which changed the chip design concept from putting transistors on a traditional plane to stacking transistors vertically to increase the density and efficiency of the chip.

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According to IBM, the technology can create 0.7-nanometer transistors, or about 7 angstroms (OH), with a chip about the size of a fingernail capable of containing nearly 100 billion transistors, or nearly double the 2-nanometer platform the company previously launched, resulting in a 50% increase in processing efficiency, or if it operates at the same efficiency, it can reduce power consumption by up to 70%.

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Behind this technology is the use of 3D Sequential Integration techniques, or three-dimensional circuit connections, in combination with the Thin Dielectric Wafer Bonding process, to bridge two Nanosheet structured wafers together using a very thin insulating layer sandwiched, allowing transistors from each wafer to be spliced and arranged vertically nested until they work together into the same CMOS circuit.

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In other words, instead of placing the spread transistor on a flat floor like a traditional chip, IBM chose to use a "stack layer" approach like a high-rise, making the same area for more transistors, and also allowing each layer to use different materials or structures, such as a first layer focusing on efficiency, another layer focusing on energy efficiency, without the need to design all layers the same.

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According to IBM, this design also allows for the use of different semiconductor materials in each layer of the transistor to independently tune the balance between performance and power consumption. It also reduces the area of SRAM memory by about 40%, which is an important part for artificial intelligence (AI) tasks that require both high bandwidth and low latency.

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Another key factor is the use of ASML's new generation of High-NA EUV machines, which have higher resolution than current generation EUV machines, allowing for more accurate generation of circuit motifs of small levels below 1 nm. It is considered a key technology for chip manufacturing in the next generation.

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However, IBM emphasizes that this 0.7-nanometer technology is still in the research and engineering demonstration stage, not yet a commercial manufacturing process, which the company sees as the cornerstone of the semiconductor industry in the future, and expects that it may take years before it is actually put into production on a large scale.

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Source: IBM

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